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MRF89XA
TABLE 3-1:
FREQUENCY BAND SETTING
FSK Mode
f rf , fsk = --- f lo
Target Channel
(MHz)
863-870
902-915
915-928
950-960
FBS1
1
0
0
1
FBS0
0
0
1
0
The formula provided in Equation 3-1 gives the
relationship between the local oscillator, and R, P and
S values, when using FSK modulation.
EQUATION 3-1:
9
8
f rf , fsk = --- × ------------- [ 75 ? ( P + 1 ) + S ]
3.2.6.1
Trimming the VCO
Hardware and Software
Tank
by
9 f xtaL
8 R + 1
To ensure that the frequency band of operation may be
f rf , ook , tx = --- × f lo – f dev
= --- × ------------- [ 75 ? ( P + 1 ) + S ] – f dev
f rf , ook , tx
f rf , ook , rx = --- × f lo – IF 2
f rf , ook , rx = --- × ------------- [ 75 ? ( P + 1 ) + S ] – IF 2
accurately addressed by the R, P, and S dividers of the
synthesizer, it is necessary to ensure that the VCO is
correctly centered. The MRF89XA built-in VCO
trimming feature makes it easy and is controlled by the
SPI interface. This tuning does not require any RF test
equipment, and can be achieved by measuring Vtune,
the voltage between the PLLN and PLLP pins (6 and 7
pins).
The VCO is centered if the voltage is within the range
of 50 ≤ Vtune(mV) ≤ 150.
This measurement should be conducted when in
Transmit mode at the center frequency (fo) of the
desired band (for example, approximately 867 MHz in
the 863-870 MHz band), with the appropriate frequency
band setting using the (FBS<1:0> bits
(GCONREG<4:3>).
If this inequality is not satisfied, adjust the VCOT<1:0>
bits (GCONREG<2:0>) from ‘ 00 ’ by monitoring Vtune.
This allows the VCO voltage to be trimmed in +60 mV
increments. If the desired voltage range is
inaccessible, the voltage may be adjusted further by
changing the tank circuit inductance value.
An increase in inductance results in an increase Vtune.
In addition, for mass production, the VCO capacitance
is piece-to-piece dependant. As such, the optimization
proposed above should be verified on several
prototypes, to ensure that the population is centered
with 100 mV.
The register associated with VCO is:
? GCONREG ( Register 2-1 ).
3.2.7 FREQUENCY CALCULATION
As illustrated in Figure 2-5 , the PLL structure com-
prises three different dividers, R, P, and S, which set
the output frequency through the LO. A second set of
3.2.8 FSK MODE REGISTERS
The registers associated with FSK mode are:
? GCONREG ( Register 2-1 )
? DMODREG ( Register 2-2 ).
OOK Mode
Due to the manner in which the baseband OOK
symbols are generated, the signal is always offset by
the FSK frequency deviation (FDVAL<7:0> as
programmed in FDEVREG<7:0>). Therefore, the
center of the transmitted OOK signal is represented by
Equation 3-2 .
EQUATION 3-2:
9
8
9 f xtaL
8 R + 1
Consequently, in Receive mode, due to the low
intermediate frequency (Low-IF) architecture of the
MRF89XA, the frequency should be configured so as to
ensure the correct low-IF receiver baseband center
frequency, IF2, as shown in Equation 3-3 .
EQUATION 3-3:
9
8
9 f xtaL
8 R + 1
As described in Section 3.4.4, Channel Filters , it is
recommended that IF2 be set to 100 kHz.
dividers is also available to allow rapid switching
between a pair of frequencies: R1/P1/S1 and R2/P2/
3.2.9
OOK MODE REGISTERS
S2. These six dividers are programmed by six indepen-
dent registers (see Register 2-7 through Register 2-
12 ), which are selected by GCONREG.
The registers associated with OOK mode are:
? GCONREG ( Register 2-1 )
? DMODREG ( Register 2-2 )
?
?
FLTHREG ( Register 2-5 )
OOKCREG ( Register 2-22 )
DS70622C-page 58
Preliminary
? 2010–2011 Microchip Technology Inc.
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